Processor architecture

Apple-CORE has refined the D-RISC processor design previously designed at the University of Amsterdam, and grouped multiple D-RISC cores together to form Microgrids. More details available here.

Technology highlights:

• dataflow scheduling to extract instruction parallelism at lower chip area and energy costs than conventional out-of-order issue in scalar and superscalar pipelines
• hardware multithreading with dynamic scheduling, with tens to hundreds of hardware threads per core instead of the few threads found in contemporary hardware multithreaded cores
• hardware concurrency management to offload thread creation, synchronization and communication away from a software operating system, and accelerate management tasks so threads become an attractive substitute to hardware SIMD

Overview article over the Apple-CORE architecture advances:

Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Irfan Uddin, and Chris Jesshope. Apple-CORE: harnessing general-purpose many-cores with hardware concurrency management. Microprocessors and Microsystems, June 2013.

Technology

Apple-CORE has produced an FPGA prototype of a D-RISC core called UTLEON3. Simultaneously, the project also produced a variety of programming tools to target Microgrids.

• UTLEON3: VHDL sources of the UTLEON3 processor
• UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs (2012 book, published by Springer)
• Simulation tools for Microgrids
• C/SL Compilers and operating system components for Microgrids
• Code generation back-end for Single-Assignment C, a functional array-oriented language.

Spawn-off projects

Apple-CORE has inspired multiple projects and forked into new initiatives:

• MGSim: generalization of the MGSim platform simulation framework to support a diversity of simulation models besides D-RISC and Microgrids
• System Virtualization Platform: the Microgrid on-chip coordination protocol between D-RISC core has been generalized to other platforms than Microgrids
• Embedded Single-Assignment C: the SAC tool chain is being made more modular and lightweight to become appropriate in accelerator-based or embedded platforms