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2013 (4)

Apple-CORE: harnessing general-purpose many-cores with hardware concurrency management Poss, R.; Lankamp, M.; Yang, Q.; Fu, J.; van Tol, M. W.; Uddin, I.; and Jesshope, C. Microprocessors and Microsystems, . June 2013.

Doi bibtex 2 downloads mark as read

@article{ poss13micpro,
  author = {Raphael Poss and Mike Lankamp and Qiang Yang and Jian Fu and Michiel W. {van Tol} and Irfan Uddin and Chris Jesshope},
  doi = {10.1016/j.micpro.2013.05.004},
  urldoi = {http://dx.doi.org/10.1016/j.micpro.2013.05.004},
  issn = {0141-9331},
  journal = {Microprocessors and Microsystems},
  month = {June},
  title = {{Apple-CORE}: harnessing general-purpose many-cores with hardware concurrency management},
  year = {2013}
}

MGSim---A simulation Environment for Multi-Core Research and Education Poss, R.; Lankamp, M.; Yang, Q.; Fu, J.; Uddin, I.; and Jesshope, C. In Proc. Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), Samos, Greece, July 2013. IEEE (to appear)
bibtex 3 downloads mark as read

@inproceedings{ poss13samos,
  address = {Samos, Greece},
  author = {Raphael Poss and Mike Lankamp and Qiang Yang and Jian Fu and Irfan Uddin and Chris Jesshope},
  booktitle = {Proc. Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS)},
  month = {July},
  note = {(to appear)},
  publisher = {IEEE},
  title = {{MGSim}---A simulation Environment for Multi-Core Research and Education},
  year = {2013}
}

MGSim---Simulation tools for multi-core processor architectures Lankamp, M.; Poss, R.; Yang, Q.; Fu, J.; Uddin, I.; and Jesshope, C. R. Technical Report arXiv:1302.1390v1 [cs.AR], University of Amsterdam, February 2013.

Paper bibtex 3 downloads mark as read

@techreport{ lankamp13mgsim,
  author = {Mike Lankamp and Raphael Poss and Qiang Yang and Jian Fu and Irfan Uddin and Chris R. Jesshope},
  institution = {University of Amsterdam},
  month = {February},
  number = {arXiv:1302.1390v1 [cs.AR]},
  title = {{MGSim}---Simulation tools for multi-core processor architectures},
  url = {http://arxiv.org/abs/1302.1390},
  year = {2013}
}

On the construction of operating systems for the Microgrid many-core architecture van Tol, M. W. Ph.D. Thesis, University of Amsterdam, 2013.

Paper bibtex mark as read

@phdthesis{ vantol13,
  author = {van Tol, Michiel W.},
  isbn = {978-90-9027317-4},
  publisher = {Gildeprint Drukkerijen},
  read = {1},
  school = {University of Amsterdam},
  title = {On the construction of operating systems for the {Microgrid} many-core architecture},
  url = {http://dare.uva.nl/record/436834},
  year = {2013}
}

2012 (7)

Apple-CORE: Microgrids of SVP cores (invited paper) Poss, R.; Lankamp, M.; Yang, Q.; Fu, J.; van Tol, M. W.; and Jesshope, C. In Niar, S., editor, Proc. 15th Euromicro Conference on Digital System Design (DSD 2012), September 2012. IEEE Computer Society

Doi bibtex 3 downloads mark as read

@inproceedings{ poss12dsd,
  author = {Raphael Poss and Mike Lankamp and Qiang Yang and Jian Fu and Michiel W. {van Tol} and Chris Jesshope},
  booktitle = {Proc. 15th Euromicro Conference on Digital System Design (DSD 2012)},
  doi = {10.1109/DSD.2012.25},
  urldoi = {http://dx.doi.org/10.1109/DSD.2012.25},
  editor = {Smail Niar},
  isbn = {978-0-7695-4798-5},
  month = {September},
  publisher = {IEEE Computer Society},
  title = {{Apple-CORE}: {Microgrids} of {SVP} cores (invited paper)},
  year = {2012}
}

Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores Uddin; Irfan, M.; Jesshope, C. R.; van Tol, M. W.; and Poss, R. In Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, of RAPIDO '12, pages 1--8, New York, NY, USA, 2012. ACM

Doi bibtex mark as read

@inproceedings{ UddJessvanTRAPIDO12,
  acmid = {2162132},
  address = {New York, NY, USA},
  author = {Uddin, M. Irfan and Jesshope, Chris R. and van Tol, Michiel W. and Poss, Raphael},
  booktitle = {Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools},
  doi = {10.1145/2162131.2162132},
  urldoi = {http://dx.doi.org/10.1145/2162131.2162132},
  isbn = {978-1-4503-1114-4},
  keywords = {automatic annotation of basic blocks with performance, estimation, performance estimation},
  location = {Paris, France},
  numpages = {8},
  pages = {1--8},
  publisher = {ACM},
  series = {RAPIDO '12},
  title = {Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores},
  year = {2012}
}

Heterogeneous integration to simplify many-core architecture simulations Poss, R.; Lankamp, M.; Uddin; Irfan, M.; Sýkora, J.; and Kafka, L. In Proc. 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, of RAPIDO '12, pages 17--24, 2012. ACM

Doi bibtex 1 download mark as read

@inproceedings{ PosLanUddRAPIDO12,
  acmid = {2162134},
  author = {Poss, Raphael and Lankamp, Mike and Uddin, M. Irfan and Sýkora, Jaroslav and Kafka, Leoš},
  booktitle = {Proc. 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools},
  doi = {10.1145/2162131.2162134},
  urldoi = {http://dx.doi.org/10.1145/2162131.2162134},
  isbn = {978-1-4503-1114-4},
  keywords = {hardware multithreading, hardware/software co-design, many-core architecture, simulation, system design, system evaluation, system-on-chip design, vertical approach},
  location = {Paris, France},
  numpages = {8},
  pages = {17--24},
  publisher = {ACM},
  series = {RAPIDO '12},
  title = {Heterogeneous integration to simplify many-core architecture simulations},
  year = {2012}
}

Lazy Reference Counting for the Microgrid Poss, R.; Grelck, C.; Herhut, S.; and Scholz, S. In Proc. 16th Workshop on on Interaction between Compilers and Computer Architectures (INTERACT'16), 2012. IEEE (to appear)
bibtex mark as read

@inproceedings{ PosGreHerINTERACT12,
  author = {Raphael Poss and Clemens Grelck and Stephan Herhut and Sven-Bodo Scholz},
  booktitle = {Proc. 16th Workshop on on Interaction between Compilers and Computer Architectures (INTERACT'16)},
  note = {(to appear)},
  publisher = {IEEE},
  title = {Lazy Reference Counting for the {Microgrid}},
  year = {2012}
}

On the realizability of hardware microthreading---Revisting the general-purpose processor interface: consequences and challenges Poss, R. Ph.D. Thesis, University of Amsterdam, 2012.

Paper bibtex mark as read

@phdthesis{ Pos12,
  author = {Raphael  Poss},
  isbn = {978-94-6108-320-3},
  publisher = {Gildeprint Drukkerijen},
  url = {http://www.raphael.poss.name/on-the-realizability-of-hardware-microthreading/},
  school = {University of Amsterdam},
  title = {On the realizability of hardware microthreading---Revisting the general-purpose processor interface: consequences and challenges},
  year = {2012}
}

SL---a "quick and dirty" but working intermediate language for SVP systems Poss, R. Technical Report arXiv:1208.4572v1 [cs.PL], University of Amsterdam, August 2012.

Paper bibtex mark as read

@techreport{ poss12sl,
  author = {Raphael  Poss},
  institution = {University of Amsterdam},
  number = {arXiv:1208.4572v1 [cs.PL]},
  title = {{SL}---a "quick and dirty" but working intermediate language for {SVP} systems},
  url = {http://arxiv.org/abs/1208.4572},
  year = {2012},
  month = {August}
}

UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs Daněk, M.; Kafka, L.; Kohout, L.; Sýkora, J.; and Bartosinski, R. of Circuits and SystemsSpringer, November 2012.

Paper bibtex buy mark as read

@book{ DanKafKoh12,
  author = {M. Daněk and L. Kafka and L. Kohout and J. Sýkora and R. Bartosinski},
  isbn = {978-1-4614-2409-3},
  month = {November},
  publisher = {Springer},
  series = {Circuits and Systems},
  title = {{UTLEON3}: Exploring Fine-Grain Multi-Threading in {FPGA}s},
  url = {http://www.springer.com/engineering/circuits+%26+systems/book/978-1-4614-2409-3},
  year = {2012}
}

2011 (5)

Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3 Sykora, J.; Kafka, L.; Danek, M.; and Kohout, L. In Proceedings of the 2011 Conference on Architecture of Computing Systems (ARCS 2011), volume 6566, of Lecture Notes in Computer Science, pages 110-121, 2011. Springer
bibtex mark as read

@inproceedings{ SykKafDanARCS11,
  author = {Jaroslav Sykora and
               Leos Kafka and
               Martin Danek and
               Lukas Kohout},
  title = {Analysis of Execution Efficiency in the Microthreaded Processor
               {UTLEON3}},
  booktitle = {Proceedings of the 2011 Conference on Architecture of Computing Systems {(ARCS 2011)}},
  series = {Lecture Notes in Computer Science},
  volume = {6566},
  publisher = {Springer},
  year = {2011},
  pages = {110-121},
  doi = {10.1007/978-3-642-19137-4_10},
  crossref = {DBLP:conf/arcs/2011},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Architecture of Computing Systems - ARCS 2011 - 24th International Conference, Como, Italy, February 24-25, 2011. Proceedings Berekovic, M.; Fornaciari, W.; Brinkschulte, U.; and Silvano, C. , editor s. Volume 6566, of Lecture Notes in Computer Science. 2011.Springer.
bibtex buy mark as read

@proceedings{ BerForBri11,
  editor = {Mladen Berekovic and
               William Fornaciari and
               Uwe Brinkschulte and
               Cristina Silvano},
  title = {Architecture of Computing Systems - ARCS 2011 - 24th International
               Conference, Como, Italy, February 24-25, 2011. Proceedings},
  booktitle = {ARCS},
  publisher = {Springer},
  series = {Lecture Notes in Computer Science},
  volume = {6566},
  year = {2011},
  isbn = {978-3-642-19136-7},
  doi = {10.1007/978-3-642-19137-4},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Concurrent Non-Deferred Reference Counting on the Microgrid: First Experiences Herhut, S.; Joslin, C.; Scholz, S‥; Poss, R.; and Grelck, C. In Haage, J.; and Moraźan, M., editor, 22nd International Symposium on Implementation and Application of Functional Languages (IFL'10), Alphen a/d Rijn, Netherlands, Revised Selected Papers, volume 6647, of Lecture Notes in Computer Science, pages 185--202, 2011. Springer-Verlag, Berlin, Heidelberg, New York to appear
bibtex mark as read

@inproceedings{ HerhJoslSchoIFL10,
  author = {S. Herhut and C. Joslin and S.B. Scholz and R. Poss and C. Grelck},
  title = {{Concurrent Non-Deferred Reference Counting on the Microgrid: First Experiences}},
  editor = {J. Haage and M. Moraźan },
  booktitle = {22nd International Symposium on
               Implementation and Application of Functional Languages (IFL'10),
               Alphen a/d Rijn, Netherlands,
               Revised Selected Papers},
  publisher = {Springer-Verlag, Berlin, Heidelberg, New York},
  series = {Lecture Notes in Computer Science},
  volume = {6647},
  number = {},
  year = {2011},
  pages = {185--202},
  isbn = {978-3-642-24275-5},
  doi = {10.1007/978-3-642-24276-2_12},
  note = {to appear},
  contents = {},
  sourceurl = {},
  topics = {SAC}
}

Fine Grained Parallelism in Recursive Function Calls Saougkos, D.; Mastoras, A.; and Manis, G. In , editor, Workshop on Languaged-Based Parallel Programming Models, 2011.
bibtex mark as read

@inproceedings{ SaougkosManisLBPPM11,
  author = {Dimitris Saougkos and Aristeidis Mastoras and George Manis },
  title = {{Fine Grained Parallelism
                        in Recursive Function Calls}},
  editor = {},
  booktitle = {Workshop on Languaged-Based Parallel Programming Models},
  publisher = {},
  series = {},
  volume = {},
  number = {},
  year = {2011},
  pages = {},
  note = {},
  contents = {},
  sourceurl = {},
  topics = {wp3}
}

Run--Time Scheduling with the` C2uTC Parallelizing Compiler Saougkos, D.; and Manis, G. In , editor, 2nd Workshop on Parallel Programming and Run--Time Management Techniques for Many--Core Architectures, in Workshop Proceedings of the 24th Conference on Computing Systems (ARCS 2011), pages 151-157, 2011. Springer
bibtex mark as read

@inproceedings{ SaougkosManisPARMA11,
  author = {Dimitris Saougkos and George Manis },
  title = {{Run--Time Scheduling with the`
                        C2uTC Parallelizing Compiler }},
  editor = {},
  booktitle = {2nd Workshop on Parallel Programming and Run--Time Management
               Techniques for Many--Core Architectures,
		in Workshop Proceedings of the 24th
		Conference on Computing Systems (ARCS 2011) },
  publisher = {Springer},
  series = {},
  volume = {},
  number = {},
  year = {2011},
  pages = {151-157},
  note = {},
  contents = {},
  sourceurl = {},
  topics = {wp3}
}

2010 (11)

Compilation of Modelica Array Computations into Single Assignment C for Efficient Execution on CUDA-enabled GPU Stavåker, K.; Rolls, D.; Guo, J.; and Fritzson, P. In , editor, 3rd International Workshop on Equation-Based Object-Oriented Languages and Tools, Oslo, Norway, October 2010.
bibtex mark as read

@inproceedings{ RollSchoJoslStavEOOLT10,
  author = {Kristian Stavåker and Daniel Rolls and Jing Guo and Peter Fritzson},
  title = {Compilation of Modelica Array Computations into Single
  Assignment C for Efficient Execution on CUDA-enabled GPU},
  editor = {},
  booktitle = {3rd International Workshop on Equation-Based Object-Oriented
  Languages and Tools, Oslo, Norway},
  publisher = {},
  series = {},
  volume = {},
  number = {},
  month = {October},
  year = {2010},
  topics = {SAC, cuda, Modelica, Openmodelica}
}

Concurrent Non-Deferred Reference Counting on the Microgrid: First Experiences Herhut, S.; and Scholz, S. Technical Report Utrecht University, Utrecht, The Netherlands., 2010.
bibtex mark as read

@techreport{ HerhSchoIFL10draft,
  author = {Stephan Herhut and Sven-Bodo Scholz},
  institution = {Utrecht University, Utrecht, The Netherlands.},
  title = {{Concurrent Non-Deferred Reference Counting on the Microgrid: First Experiences}},
  year = {2010},
  type = {{In: IFL'10: Draft Proceedings of the 22nd Symposium on Implementation and Application of Functional Languages.}}
}

Instruction Set Extensions for Multi-Threading in LEON3 Danek, M.; Kafka, L.; Kohout, L.; and Sykora, J. In et al., Z.K., editor, Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS2010, pages 237--242, 2010. IEEE
bibtex mark as read

@inproceedings{ DaneKafkKoho10,
  author = {Danek, M. and Kafka, L. and Kohout, L. and Sykora, J.},
  title = {Instruction Set Extensions for Multi-Threading in {LEON3}},
  booktitle = {Proceedings of the 13th {IEEE} Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS2010},
  pages = {237--242},
  editor = {Z. Kotasek et al.},
  publisher = {IEEE},
  isbn = {978-1-4244-6610-8},
  year = {2010}
}

Making multi-cores mainstream - from security to scalability Jesshope, C.; Hicks, M.; Lankamp, M.; Poss, R.; and Zhang, L. In Parallel Computing: from Multi-cores and GPUs to Petascale, pages 16 - 31, May 2010. IOS Press
bibtex mark as read

@inproceedings{ JessHicksLankPARCO.09,
  title = {Making multi-cores mainstream - from security to scalability},
  booktitle = {Parallel Computing: from Multi-cores and GPUs to Petascale},
  author = {Jesshope, Chris and Hicks, Michael and Lankamp, Mike and Poss, Raphael and Zhang, Li},
  publisher = {IOS Press},
  pages = {16 - 31},
  locaton = {Amsterdam},
  isbn = {978-1-60750-529-7},
  month = {May},
  year = {2010}
}

On the Compilation of a Language for General Concurrent Target Architectures Bernard, T.; Grelck, C.; and Jesshope, C. Parallel Processing Letters, 20. June 2010.
bibtex mark as read

@article{ a-bernard-ppl-10,
  author = {Bernard, Thomas and Grelck, Clemens and Jesshope, Chris},
  title = {{O}n the {C}ompilation of a {L}anguage for {G}eneral {C}oncurrent
    {T}arget {A}rchitectures},
  journal = {Parallel Processing Letters},
  year = {2010},
  volume = {20},
  month = {June},
  date-modified = {2010-02-02 20:21:40 +0100},
  issue = {2},
  publisher = {World Scientific}
}

On the Compilation of a Parallel Language targeting the Self-adaptive Virtual Processor Bernard, T. A.M. Ph.D. Thesis, University of Amsterdam, 2010.

Paper bibtex mark as read

@phdthesis{ bernard10,
  author = {Thomas A. M. Bernard},
  isbn = {978-90-9026006-8},
  school = {University of Amsterdam},
  title = {On the Compilation of a Parallel Language targeting the Self-adaptive Virtual Processor},
  url = {http://dare.uva.nl/record/370096},
  year = {2010}
}

Resource-agnostic Programming for Many-core Microgrids Bernard, T.; Grelck, C.; Hicks, M.; Jesshope, C.; and Poss, R. In 4th Workshop on Highly Parallel Processing on a Chip, 2010.
bibtex mark as read

@inproceedings{ BernGrelHickHPPC.10,
  author = {Bernard, Thomas and Grelck, Clemens and Hicks, Michael and Jesshope, Chris and Poss, R},
  booktitle = {4th Workshop on Highly Parallel Processing on a Chip},
  title = {Resource-agnostic {P}rogramming for {M}any-core {M}icrogrids},
  year = {2010}
}

Single Assignment C Tutorial. PPoPP 2010, Bangalore, India Scholz, S.; Herhut, S.; Grelck, C.; and Penczek, F. Technical Report 498, School of Computer Science, University of Hertfordshire, 2010.
bibtex mark as read

@techreport{ SchoHerhGrel10,
  author = {Scholz, Sven-Bodo and Herhut, Stephan and Grelck, Clemens and Penczek, Frank},
  institution = {School of Computer Science, University of Hertfordshire},
  number = {498},
  title = {{S}ingle {A}ssignment {C} Tutorial. PPoPP 2010, Bangalore, India},
  year = {2010}
}

Thread-Local Stacks, a Light-Weight Alternative to Thread-Local Heaps Herhut, S.; Joslin, C.; and Scholz, S. In , editor, 15th Workshop on Compilers for Parallel Computing (CPC'10), Vienna University of Technology, Vienna, Austria, 2010.
bibtex mark as read

@inproceedings{ HerhJoslSchoCPC10,
  author = {Stephan Herhut and Carl Joslin and Sven-Bodo Scholz},
  title = {{Thread-Local Stacks, a Light-Weight Alternative to Thread-Local
                Heaps}},
  editor = {},
  booktitle = {15th Workshop on Compilers for Parallel Computing (CPC'10),
               Vienna University of Technology, Vienna, Austria},
  publisher = {},
  series = {},
  volume = {},
  number = {},
  year = {2010},
  pages = {},
  note = {},
  contents = {},
  sourceurl = {},
  topics = {SAC}
}

Towards Scalable I/O on a Many-core Architecture Hicks, M. A.; van Tol, M. W.; and Jesshope, C. R. In International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), pages 341-348, July 2010. IEEE
bibtex mark as read

@inproceedings{ HickvTolJessSAMOS.10,
  title = {Towards {S}calable {I/O} on a {M}any-core {A}rchitecture},
  booktitle = {International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS)},
  author = {Michael A. Hicks and Michiel W. van Tol and Chris R. Jesshope},
  publisher = {IEEE},
  month = {July},
  pages = {341-348},
  isbn = {978-1-4244-7937-5},
  year = {2010}
}

Unibench: A Tool for Automated and Collaborative Benchmarking Rolls, D.; Joslin, C.; and Scholz, S. In 18th IEEE International Conference on Program Comprehension, June 2010. IEEE Computer Society
bibtex mark as read

@inproceedings{ RollJoslSchoICPC10,
  author = {Daniel Rolls and Carl Joslin and Sven-Bodo Scholz},
  title = {Unibench: A Tool for Automated and Collaborative Benchmarking},
  booktitle = {18th IEEE International Conference on Program Comprehension},
  publisher = {IEEE Computer Society},
  year = {2010},
  month = {June},
  topics = {unibench}
}

2009 (9)

Compiling the Functional Data-Parallel Language sac for Microgrids of Self-Adaptive Virtual Processors Grelck, C.; Herhut, S.; Jesshope, C.; Joslin, C.; Lankamp, M.; Scholz, S.; and Shafarenko, A. In , editor, 14th Workshop on Compilers for Parallel Computing (CPC'09), IBM Research Center, Zurich, Switzerland, 2009.
bibtex mark as read

@inproceedings{ GrelJessJoslCPC09,
  author = {Clemens Grelck and Stephan Herhut and Chris Jesshope and
               Carl Joslin and Mike Lankamp and Sven-Bodo Scholz
               and Alex Shafarenko},
  title = {{Compiling the Functional Data-Parallel Language sac
                for Microgrids of Self-Adaptive Virtual Processors}},
  editor = {},
  booktitle = {14th Workshop on Compilers for Parallel Computing (CPC'09),
               IBM Research Center, Zurich, Switzerland},
  publisher = {},
  series = {},
  volume = {},
  number = {},
  year = {2009},
  pages = {},
  note = {},
  contents = {},
  sourceurl = {},
  topics = {SAC}
}

Controlling Chaos --- On Safe Side-Effects in Data-Parallel Operations Herhut, S.; Scholz, S.; and Grelck, C. In , editor, Annual Symposium on Principles of Programming Languages (POPL), 4th Workshop on Declarative Aspects of Multicore Programming (DAMP'09), Savannah, Georgia, USA, pages 59--67, 2009. ACM Press, New York City, New York, USA
bibtex mark as read

@inproceedings{ HerhSchoGrelDAMP09,
  author = {Stephan Herhut and Sven-Bodo Scholz and Clemens Grelck},
  title = {{Controlling Chaos --- On Safe Side-Effects in Data-Parallel
                Operations}},
  editor = {},
  booktitle = {Annual Symposium on Principles of Programming Languages (POPL),
               4th Workshop on Declarative Aspects of Multicore
               Programming (DAMP'09),
               Savannah, Georgia, USA},
  publisher = {ACM Press, New York City, New York, USA},
  series = {},
  volume = {},
  number = {},
  year = {2009},
  pages = {59--67},
  isbn = {978-1-60558-417-1},
  doi = {http://doi.acm.org/10.1145/1481839.1481847},
  note = {},
  contents = {},
  sourceurl = {},
  topics = {SAC}
}

Evaluating CMPs and their memory architecture Jesshope, C.; Lankamp, M.; and Zhang, L. In Berekovic, M.; Muller-Schoer, C.; Hochberger, C.; and Wong, S., editor, Proc. Architecture of Computing Systems, pages 246-257, 2009.
bibtex mark as read

@inproceedings{ JessLankZhanARCS09,
  author = {C. Jesshope and M. Lankamp and L. Zhang},
  title = {{Evaluating CMPs and their memory architecture}},
  booktitle = {Proc. Architecture of Computing Systems},
  year = {2009},
  editor = {M. Berekovic and C. Muller-Schoer and C. Hochberger and S. Wong},
  pages = {246-257},
  isbn = {}
}

Implementation and Evaluation of a Microthread Architecture Bousias, K.; Guang, L.; Jesshope, C‥; and Lankamp, M. Journal of Systems Architecture, 55(3):149-161. 2009.
bibtex mark as read

@article{ BousGuanJessJSA08,
  author = {K. Bousias and L. Guang and C.R. Jesshope and M. Lankamp },
  title = {{Implementation and Evaluation of a Microthread Architecture}},
  journal = {Journal of Systems Architecture},
  year = {2009},
  editor = {},
  volume = {55},
  number = {3},
  pages = {149-161},
  isbn = {},
  publisher = {}
}

Numerical simulations of unsteady shock wave interactions using SAC and Fortran-90 Kudryavtsev, A.; Rolls, D.; Scholz, S.; and Shafarenko, A. In , editor, 10th International Conference on Parallel Computing Technologies (PaCT'09), volume 5083, of Lecture Notes in Computer Science, pages 445--456, 2009. Springer-Verlag, Berlin, Heidelberg, New York
bibtex mark as read

@inproceedings{ RollSchoKudrPACT09,
  author = {Alexei Kudryavtsev and Daniel Rolls and Sven-Bodo Scholz
               and Alex Shafarenko},
  title = {{Numerical simulations of unsteady shock wave interactions
                using SAC and Fortran-90}},
  editor = {},
  booktitle = {10th International Conference on Parallel Computing
               Technologies (PaCT'09)},
  publisher = {Springer-Verlag, Berlin, Heidelberg, New York},
  series = {Lecture Notes in Computer Science},
  volume = {5083},
  number = {},
  year = {2009},
  pages = {445--456},
  note = {},
  contents = {},
  sourceurl = {},
  topics = {SAC}
}

Specifying Loop Transformations for C2uTC Source to Source Compiler Saougkos, D.; Evgenidou, D.; and Manis, G. In , editor, 14th Workshop on Compilers for Parallel Computing (CPC'09), IBM Research Center, Zurich, Switzerland, 2009.
bibtex mark as read

@inproceedings{ SaougkosManisCPC09,
  author = {Dimitris Saougkos and Despina Evgenidou and George Manis },
  title = {{Specifying Loop Transformations
                        for C2uTC Source to Source Compiler }},
  editor = {},
  booktitle = {14th Workshop on Compilers for Parallel Computing (CPC'09),
               IBM Research Center, Zurich, Switzerland},
  publisher = {},
  series = {},
  volume = {},
  number = {},
  year = {2009},
  pages = {},
  note = {},
  contents = {},
  sourceurl = {},
  topics = {wp3}
}

The implementation of an SVP many-core processor and the evaluation of its memory architecture Jesshope, C.; Lankamp, M.; and Zhang, L. In Special Interest Group on Computer Architecture (SIGARCH), volume 37, of LNCS, pages 38--45, 2009. ACM

Doi bibtex mark as read

@inproceedings{ jessopesig09,
  author = {Jesshope, Chris and Lankamp, Mike and Zhang, Li},
  booktitle = {Special Interest Group on Computer Architecture (SIGARCH)},
  doi = {10.1145/1577129.1577136},
  urldoi = {http://dx.doi.org/10.1145/1577129.1577136},
  pages = {38--45},
  publisher = {ACM},
  series = {LNCS},
  title = {The implementation of an SVP many-core processor and the evaluation of its memory architecture},
  volume = {37},
  year = {2009}
}

Truly Nested Data-Parallelism. Compiling SAC to the Microgrid Architecture Herhut, S.; Joslin, C.; Scholz, S.; and Grelck, C. Technical Report SHU-TR-CS-2009-09-1, Seton Hall University, South Orange, NJ, USA., 2009.
bibtex mark as read

@techreport{ HerhJoslSchoIFL09draft,
  author = {Stephan Herhut and Carl Joslin and Sven-Bodo Scholz and Clemens Grelck},
  institution = {Seton Hall University, South Orange, NJ, USA.},
  number = {SHU-TR-CS-2009-09-1},
  title = {Truly Nested Data-Parallelism. Compiling SAC to the Microgrid Architecture},
  year = {2009},
  type = {In: IFL ’09: Draft Proceedings of the 21st Symposium on Implementation and Application of Functional Languages.}
}

Unibench: The Swiss Army Knife for Collaborative, Automated Benchmarking Rolls, D.; Herhut, S.; Joslin, C.; and Scholz, S. Technical Report SHU-TR-CS-2009-09-1, Seton Hall University, South Orange, NJ, USA., 2009.
bibtex mark as read

@techreport{ RollHerhJoslIFL09draft,
  author = {Daniel Rolls and Stephan Herhut and Carl Joslin and Sven-Bodo Scholz},
  institution = {Seton Hall University, South Orange, NJ, USA.},
  number = {SHU-TR-CS-2009-09-1},
  title = {Unibench: The Swiss Army Knife for Collaborative, Automated Benchmarking},
  year = {2009},
  type = {In: IFL ’09: Draft Proceedings of the 21st Symposium on Implementation and Application of Functional Languages.}
}

2008 (7)

A general model of concurrency and its implementation as many-core dynamic RISC processors Bernard, T.; Bousias, K.; Guang, L.; Jesshope, C. R.; Lankamp, M.; van Tol, M. W.; and Zhang, L. In Najjar, W.; and Blume, H., editor, Proc. Intl. Conf. on Embedded Computer Systems: Architecture, Modeling and Simulation, SAMOS-2008, pages 1-9, 2008.
bibtex mark as read

@inproceedings{ BernBousGuanSAMOS08,
  author = {T. Bernard and K. Bousias and L. Guang and C. R. Jesshope and M. Lankamp and M. W. van Tol and L. Zhang},
  title = {{A general model of concurrency and its implementation as many-core dynamic RISC processors}},
  booktitle = {Proc. Intl. Conf. on Embedded Computer Systems: Architecture, Modeling and Simulation, SAMOS-2008},
  year = {2008},
  editor = {W. Najjar and H. Blume},
  pages = {1-9},
  isbn = {978-1-4244-1985-2}
}

A model for the design and programming of multi-cores Jesshope, C. Advances in Parallel Computing, High Performance Computing and Grids in Action(16):37-55. 2008.
bibtex mark as read

@article{ JesshopeAPC08,
  author = {Chris Jesshope},
  title = {{A model for the design and programming of multi-cores}},
  journal = {Advances in Parallel Computing},
  year = {2008},
  editor = {L. Grandinetti},
  volume = {High Performance Computing and Grids in Action},
  number = {16},
  pages = {37-55},
  isbn = {978-1-58603-839-7},
  publisher = {IOS Press}
}

An architecture and protocol for the management of resources in ubiquitous and heterogeneous systems based on the SVP model of concurrency Jesshope, C.; Philippe, J.; and van Tol, M. In , editor, Embedded Computer Systems: Architectures, Modeling, and Simulation, pages 218-228, 2008.
bibtex mark as read

@inproceedings{ JessPhilTolLNCS08,
  author = {Chris Jesshope and Jean-Marc Philippe and Michiel van Tol},
  title = {{An architecture and protocol for the management of resources in ubiquitous and heterogeneous systems based on the SVP model of concurrency}},
  booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation},
  year = {2008},
  editor = {},
  pages = {218-228},
  isbn = {978-3-540-70549-9}
}

Compiling the Functional Data-Parallel Language SaC for the Self-Adaptive Virtual Processor Architecture Herhut, S.; Joslin, C.; and Scholz, S. Technical Report 482, School of Computer Science, University of Hertfordshire, 2008.
bibtex mark as read

@techreport{ HerhJoslScho08,
  author = {Stephan Herhut and Carl Joslin and Sven-Bodo Scholz},
  institution = {School of Computer Science, University of Hertfordshire},
  number = {482},
  title = {Compiling the Functional Data-Parallel Language SaC for the Self-Adaptive Virtual Processor Architecture},
  year = {2008}
}

Concurrency Engineering Jesshope, C.; and Shafarenko, A. In , editor, Proc. 13th IEEE Asia-Pacific Computer Systems Architecture Conference, 2008.
bibtex mark as read

@inproceedings{ JessShafACSAC08,
  author = {Chris Jesshope and Alex Shafarenko},
  title = {{Concurrency Engineering}},
  editor = {},
  booktitle = {Proc. 13th IEEE Asia-Pacific Computer Systems Architecture Conference},
  publisher = {},
  series = {},
  volume = {},
  number = {},
  year = {2008},
  pages = {},
  isbn = {978-1-4244-2683-6},
  note = {},
  contents = {},
  sourceurl = {},
  topics = {}
}

Operating systems in silicon and the dynamic management of resources in many-core chips Jesshope, C. Parallel Processing Letters, 18(2):257-274. 2008.
bibtex mark as read

@article{ JessPPL08,
  author = {Chris Jesshope},
  title = {{Operating systems in silicon and the dynamic management of resources in many-core chips}},
  journal = {Parallel Processing Letters},
  year = {2008},
  editor = {},
  volume = {18},
  number = {2},
  pages = {257-274},
  isbn = {},
  publisher = {},
  isbn = {}
}

The verification of the on-chip COMA cache coherence protocol D.Vu, T.; Zhang, L.; and Jesshope, C. R. In , editor, International Conference on Algebraic Methodology and Software Technology, pages 413-429, 2008.
bibtex mark as read

@inproceedings{ VuZhanJessAMAST08,
  author = {T. D.Vu and L. Zhang and C. R. Jesshope},
  title = {{The verification of the on-chip COMA cache coherence protocol}},
  editor = {},
  booktitle = {International Conference on Algebraic Methodology and Software Technology},
  publisher = {},
  series = {},
  volume = {},
  number = {},
  year = {2008},
  pages = {413-429},
  isbn = {978-3-540-79979-5},
  note = {},
  contents = {},
  sourceurl = {},
  topics = {}
}

1996 (1)

Dynamic scheduling in RISC architectures Bolychevsky, A.; Jesshope, C. R.; and Muchnick, V. B. IEE Trans. E, Computers and Digital Techniques, 143:309-317. 1996.
bibtex mark as read

@article{ BolyJessMuchIEET96,
  author = { A Bolychevsky and C R Jesshope and V B Muchnick },
  title = {{Dynamic scheduling in RISC architectures}},
  journal = {IEE Trans. E, Computers and Digital Techniques},
  year = {1996},
  editor = {},
  volume = {143},
  number = {},
  pages = {309-317},
  isbn = {},
  publisher = {}
}