Publications

  2013 (4)
Apple-CORE: harnessing general-purpose many-cores with hardware concurrency management Poss, R.; Lankamp, M.; Yang, Q.; Fu, J.; van Tol, M. W.; Uddin, I.; and Jesshope, C. Microprocessors and Microsystems, . June 2013.
 [004]Doi   bibtex   2 downloads mark as read
MGSim---A simulation Environment for Multi-Core Research and Education Poss, R.; Lankamp, M.; Yang, Q.; Fu, J.; Uddin, I.; and Jesshope, C. In Proc. Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), Samos, Greece, July 2013. IEEE (to appear)
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MGSim---Simulation tools for multi-core processor architectures Lankamp, M.; Poss, R.; Yang, Q.; Fu, J.; Uddin, I.; and Jesshope, C. R. Technical Report arXiv:1302.1390v1 [cs.AR], University of Amsterdam, February 2013.
 [1390]Paper   bibtex   3 downloads mark as read
On the construction of operating systems for the Microgrid many-core architecture van Tol, M. W. Ph.D. Thesis, University of Amsterdam, 2013.
 [nl/record/436834]Paper   bibtex mark as read
  2012 (7)
Apple-CORE: Microgrids of SVP cores (invited paper) Poss, R.; Lankamp, M.; Yang, Q.; Fu, J.; van Tol, M. W.; and Jesshope, C. In Niar, S., editor, Proc. 15th Euromicro Conference on Digital System Design (DSD 2012), September 2012. IEEE Computer Society
 [25]Doi   bibtex   3 downloads mark as read
Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores Uddin; Irfan, M.; Jesshope, C. R.; van Tol, M. W.; and Poss, R. In Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, of RAPIDO '12, pages 1--8, New York, NY, USA, 2012. ACM
 [2162132]Doi   bibtex mark as read
Heterogeneous integration to simplify many-core architecture simulations Poss, R.; Lankamp, M.; Uddin; Irfan, M.; Sýkora, J.; and Kafka, L. In Proc. 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, of RAPIDO '12, pages 17--24, 2012. ACM
 [2162134]Doi   bibtex   1 download mark as read
Lazy Reference Counting for the Microgrid Poss, R.; Grelck, C.; Herhut, S.; and Scholz, S. In Proc. 16th Workshop on on Interaction between Compilers and Computer Architectures (INTERACT'16), 2012. IEEE (to appear)
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On the realizability of hardware microthreading---Revisting the general-purpose processor interface: consequences and challenges Poss, R. Ph.D. Thesis, University of Amsterdam, 2012.
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SL---a "quick and dirty" but working intermediate language for SVP systems Poss, R. Technical Report arXiv:1208.4572v1 [cs.PL], University of Amsterdam, August 2012.
 [4572]Paper   bibtex mark as read
UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs Daněk, M.; Kafka, L.; Kohout, L.; Sýkora, J.; and Bartosinski, R. of Circuits and SystemsSpringer, November 2012.
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  2011 (5)
Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3 Sykora, J.; Kafka, L.; Danek, M.; and Kohout, L. In Proceedings of the 2011 Conference on Architecture of Computing Systems (ARCS 2011), volume 6566, of Lecture Notes in Computer Science, pages 110-121, 2011. Springer
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Architecture of Computing Systems - ARCS 2011 - 24th International Conference, Como, Italy, February 24-25, 2011. Proceedings Berekovic, M.; Fornaciari, W.; Brinkschulte, U.; and Silvano, C. , editor s. Volume 6566, of Lecture Notes in Computer Science. 2011.Springer.
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Concurrent Non-Deferred Reference Counting on the Microgrid: First Experiences Herhut, S.; Joslin, C.; Scholz, S‥; Poss, R.; and Grelck, C. In Haage, J.; and Moraźan, M., editor, 22nd International Symposium on Implementation and Application of Functional Languages (IFL'10), Alphen a/d Rijn, Netherlands, Revised Selected Papers, volume 6647, of Lecture Notes in Computer Science, pages 185--202, 2011. Springer-Verlag, Berlin, Heidelberg, New York to appear
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Fine Grained Parallelism in Recursive Function Calls Saougkos, D.; Mastoras, A.; and Manis, G. In , editor, Workshop on Languaged-Based Parallel Programming Models, 2011.
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Run--Time Scheduling with the` C2uTC Parallelizing Compiler Saougkos, D.; and Manis, G. In , editor, 2nd Workshop on Parallel Programming and Run--Time Management Techniques for Many--Core Architectures, in Workshop Proceedings of the 24th Conference on Computing Systems (ARCS 2011), pages 151-157, 2011. Springer
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  2010 (11)
Compilation of Modelica Array Computations into Single Assignment C for Efficient Execution on CUDA-enabled GPU Stavåker, K.; Rolls, D.; Guo, J.; and Fritzson, P. In , editor, 3rd International Workshop on Equation-Based Object-Oriented Languages and Tools, Oslo, Norway, October 2010.
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Concurrent Non-Deferred Reference Counting on the Microgrid: First Experiences Herhut, S.; and Scholz, S. Technical Report Utrecht University, Utrecht, The Netherlands., 2010.
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Instruction Set Extensions for Multi-Threading in LEON3 Danek, M.; Kafka, L.; Kohout, L.; and Sykora, J. In et al., Z.K., editor, Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS2010, pages 237--242, 2010. IEEE
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Making multi-cores mainstream - from security to scalability Jesshope, C.; Hicks, M.; Lankamp, M.; Poss, R.; and Zhang, L. In Parallel Computing: from Multi-cores and GPUs to Petascale, pages 16 - 31, May 2010. IOS Press
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On the Compilation of a Language for General Concurrent Target Architectures Bernard, T.; Grelck, C.; and Jesshope, C. Parallel Processing Letters, 20. June 2010.
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On the Compilation of a Parallel Language targeting the Self-adaptive Virtual Processor Bernard, T. A.M. Ph.D. Thesis, University of Amsterdam, 2010.
 [nl/record/370096]Paper   bibtex mark as read
Resource-agnostic Programming for Many-core Microgrids Bernard, T.; Grelck, C.; Hicks, M.; Jesshope, C.; and Poss, R. In 4th Workshop on Highly Parallel Processing on a Chip, 2010.
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Single Assignment C Tutorial. PPoPP 2010, Bangalore, India Scholz, S.; Herhut, S.; Grelck, C.; and Penczek, F. Technical Report 498, School of Computer Science, University of Hertfordshire, 2010.
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Thread-Local Stacks, a Light-Weight Alternative to Thread-Local Heaps Herhut, S.; Joslin, C.; and Scholz, S. In , editor, 15th Workshop on Compilers for Parallel Computing (CPC'10), Vienna University of Technology, Vienna, Austria, 2010.
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Towards Scalable I/O on a Many-core Architecture Hicks, M. A.; van Tol, M. W.; and Jesshope, C. R. In International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), pages 341-348, July 2010. IEEE
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Unibench: A Tool for Automated and Collaborative Benchmarking Rolls, D.; Joslin, C.; and Scholz, S. In 18th IEEE International Conference on Program Comprehension, June 2010. IEEE Computer Society
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  2009 (9)
Compiling the Functional Data-Parallel Language sac for Microgrids of Self-Adaptive Virtual Processors Grelck, C.; Herhut, S.; Jesshope, C.; Joslin, C.; Lankamp, M.; Scholz, S.; and Shafarenko, A. In , editor, 14th Workshop on Compilers for Parallel Computing (CPC'09), IBM Research Center, Zurich, Switzerland, 2009.
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Controlling Chaos --- On Safe Side-Effects in Data-Parallel Operations Herhut, S.; Scholz, S.; and Grelck, C. In , editor, Annual Symposium on Principles of Programming Languages (POPL), 4th Workshop on Declarative Aspects of Multicore Programming (DAMP'09), Savannah, Georgia, USA, pages 59--67, 2009. ACM Press, New York City, New York, USA
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Evaluating CMPs and their memory architecture Jesshope, C.; Lankamp, M.; and Zhang, L. In Berekovic, M.; Muller-Schoer, C.; Hochberger, C.; and Wong, S., editor, Proc. Architecture of Computing Systems, pages 246-257, 2009.
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Implementation and Evaluation of a Microthread Architecture Bousias, K.; Guang, L.; Jesshope, C‥; and Lankamp, M. Journal of Systems Architecture, 55(3):149-161. 2009.
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Numerical simulations of unsteady shock wave interactions using SAC and Fortran-90 Kudryavtsev, A.; Rolls, D.; Scholz, S.; and Shafarenko, A. In , editor, 10th International Conference on Parallel Computing Technologies (PaCT'09), volume 5083, of Lecture Notes in Computer Science, pages 445--456, 2009. Springer-Verlag, Berlin, Heidelberg, New York
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Specifying Loop Transformations for C2uTC Source to Source Compiler Saougkos, D.; Evgenidou, D.; and Manis, G. In , editor, 14th Workshop on Compilers for Parallel Computing (CPC'09), IBM Research Center, Zurich, Switzerland, 2009.
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The implementation of an SVP many-core processor and the evaluation of its memory architecture Jesshope, C.; Lankamp, M.; and Zhang, L. In Special Interest Group on Computer Architecture (SIGARCH), volume 37, of LNCS, pages 38--45, 2009. ACM
 [1577136]Doi   bibtex mark as read
Truly Nested Data-Parallelism. Compiling SAC to the Microgrid Architecture Herhut, S.; Joslin, C.; Scholz, S.; and Grelck, C. Technical Report SHU-TR-CS-2009-09-1, Seton Hall University, South Orange, NJ, USA., 2009.
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Unibench: The Swiss Army Knife for Collaborative, Automated Benchmarking Rolls, D.; Herhut, S.; Joslin, C.; and Scholz, S. Technical Report SHU-TR-CS-2009-09-1, Seton Hall University, South Orange, NJ, USA., 2009.
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  2008 (7)
A general model of concurrency and its implementation as many-core dynamic RISC processors Bernard, T.; Bousias, K.; Guang, L.; Jesshope, C. R.; Lankamp, M.; van Tol, M. W.; and Zhang, L. In Najjar, W.; and Blume, H., editor, Proc. Intl. Conf. on Embedded Computer Systems: Architecture, Modeling and Simulation, SAMOS-2008, pages 1-9, 2008.
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A model for the design and programming of multi-cores Jesshope, C. Advances in Parallel Computing, High Performance Computing and Grids in Action(16):37-55. 2008.
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An architecture and protocol for the management of resources in ubiquitous and heterogeneous systems based on the SVP model of concurrency Jesshope, C.; Philippe, J.; and van Tol, M. In , editor, Embedded Computer Systems: Architectures, Modeling, and Simulation, pages 218-228, 2008.
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Compiling the Functional Data-Parallel Language SaC for the Self-Adaptive Virtual Processor Architecture Herhut, S.; Joslin, C.; and Scholz, S. Technical Report 482, School of Computer Science, University of Hertfordshire, 2008.
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Concurrency Engineering Jesshope, C.; and Shafarenko, A. In , editor, Proc. 13th IEEE Asia-Pacific Computer Systems Architecture Conference, 2008.
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Operating systems in silicon and the dynamic management of resources in many-core chips Jesshope, C. Parallel Processing Letters, 18(2):257-274. 2008.
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The verification of the on-chip COMA cache coherence protocol D.Vu, T.; Zhang, L.; and Jesshope, C. R. In , editor, International Conference on Algebraic Methodology and Software Technology, pages 413-429, 2008.
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  1996 (1)
Dynamic scheduling in RISC architectures Bolychevsky, A.; Jesshope, C. R.; and Muchnick, V. B. IEE Trans. E, Computers and Digital Techniques, 143:309-317. 1996.
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